A phase change memory element is a memory element for storing information using the characteristics of electric conductivity or a resistance difference between a crystalline phase and an amorphous phase of a specific phase change material. The phase change memory element forms a memory cell electrically connected to a transistor element or the like, formed on a semiconductor substrate for addressing and read/write operations of the device. In the memory element, information is stored using a conductivity difference in accordance with the phase change of a region of a memory layer.
FIG. 1A and FIG. 1B illustrate a conventional phase change memory cell 10. As seen in FIG. 1A, the phase change memory cell 10 includes a phase change material 14 between a top electrode 12 and a bottom electrode 18. To increase the current density and, thereby, improve the efficiency of heating of the phase change material 14, the bottom electrode 18 may be connected to the phase change material 14 through a bottom electrode contact (BEC) 16 that has reduced surface area in comparison to the bottom electrode 18. An access transistor 20 may be connected to the bottom electrode 18 and controlled by a word line.
As seen in FIGS. 1A, 1B and 2, the phase change memory cell 10 operates such that a current flowing through the phase change material 14 electrically heats a phase change region, and the structure of the phase change material 14 is reversibly changed to a crystalline state (FIG. 1A) or an amorphous state (FIG. 1B) to store information. In FIG. 1B, the region of the phase change material 14 that changes state to an amorphous state is illustrated by the cross-hatched region adjacent the BEC 16. The stored information can be read by flowing a relatively low current through the phase change region and measuring the resistance of the phase change material. Thus, FIG. 2 illustrates a conventional phase change memory cell 10 where a cell transistor 20 is controlled by a word line WL to control the flow of current ICELL from a bit line BL through the variable resistance C provided by the phase change material.
In setting the region of the phase change material 14 to an amorphous state or a crystalline state, different pulses may be used to control the heating of the phase change material 14. As seen in FIG. 3, a high temperature short duration heating cycle 35 is used to reset the phase change material 14 to an amorphous state and a longer duration lower temperature heating cycle 36 is used to set the phase change material 14 to a crystalline state. In particular, in the short duration cycle 35, the phase change material 14 is heated to a temperature above the melting point, Tm, of the phase change material 14 and then quickly cooled, e.g., within a few nanoseconds, to create an amorphous region in the phase change material 14. In the longer duration cycle 36, the phase change material 14 is heated to a temperature above a crystallizing point, Tx, and below the melting point, Tm, of the phase change material 14 and maintained at that temperature for a predetermined time before cooling to create a crystallized region in the phase change material 14. Thus, the temperature is maintained within a set window of above the crystallizing temperature Tx and below the melting temperature Tm.
FIG. 4 illustrates various current waveforms for programming phase-change memories. In particular, as seen in FIG. 4, the reset current is of shorter duration but greater amplitude than the set current. If multiple memory cells (e.g., more than 16 bits) are reset simultaneously, the peak current may exceed the capability of the power supply, which may result in fluctuations in the output of the power supply. Typically, the number of memory cells in a block of memory cells that are simultaneously programmed (set and reset) has been limited by the reset current considerations.
Various techniques for programming phase-change memory cells are discussed, for example, in U.S. Pat. Nos. 6,545,907; 6,075,719; and 6,487,113.